CV

Education & Training

• Stanford University, Stanford, CA, USA (2022 – present)
  • Postdoctoral Scholar in Electrical Engineering
  • Advisor: Prof. Subhasish Mitra & Prof. H.-S. Philip Wong
• Huazhong University of Science and Technology, Wuhan City, Hubei Province, China (2015 – 2020)
  • Ph.D. in Microelectronics and Solid-State Electronics
  • Advisor: Prof. Yanqing Wu
  • Thesis Title: Low-power and high-performance electronic devices based on ultra-thin indium-tin-oxide</a>
• Huazhong University of Science and Technology, Wuhan City, Hubei Province, China (2011 – 2015)
  • B.Tech. (Hons.) in Electronic Science and Technology

Employment

• Hunan University, Changsha City, Hunan Province, China (2020 – 2022)
  • Associate Professor, Material Science and Technology

Research experience

• High-performance Carbon Nanotube Transistor
  • First time to integrate dopants in extension region for CNT p-MOSFET with densely aligned CNTs (Symp. VLSI Tech. 2023, Equal Contribution).
  • Developed a self-aligned process for high-performance CNT p-MOSFET with sub-20nm dopedextensions (IEDM 2023, First Author & Corresponding author).
  • Introduced and simulated a contact-anchoring process flow to release the CNT channel in the first nanosheet FETs built on an array of dense aligned CNTs (Symp. VLSI Tech. 2024).
  • Demonstrated the best CNT NMOS with barrier booster and achieved iso-performance CNT NMOS and PMOS on densely aligned CNTs (IEDM 2024, First Author & Corresponding author).
• Gain-cell for On-Chip Memory
  • Co-developed material synthesis and process flow for gain cell memory using indium-tin-oxide (Symp. VLSI Tech. 2023).
  • Led the heterogeneous integration process and device design for hybrid 2T nMOS/pMOS gain cell memory with indium-tin-oxide and carbon nanotube transistors (EDL 2023, Equal Contribution).
• Two-dimensional Material Synthesis, Electronics, and Optoelectronics
  • Designed 2D heterostructure for reconfigurable artificial synapse (ACS Applied Materials & Interfaces 2023, Corresponding Author).
  • Synthesized 2D heterostructure by chemical-vapor deposition for nano-photodetector with recordhigh detectivity (Nano Research 2024, Corresponding Author).
  • Using 2D ferroelectric material to realize processing-in-sensor and computing-in-memory for AI vision system (Science Bulletin 2024, Corresponding Author).
• Low-power and high-performance electronic devices based on ultra-thin indium-tin-oxide
  • Co-designing materials and device geometry, enabling the first demonstration of indium-tin-oxide (ITO) transistor with excellent short-channel immunity (Nature Materials 2019, First Author).
  • First demonstration of 15-nm channel length ITO transistor and inverter design for high-speed ring oscillator based on it (IEDM 2019, First Author).
  • Led the device design and process development for ITO Radio-Frequency transistor on flexible substrate (IEDM 2019).
  • Contact engineering to achieve low contact resistance of 162 Ω·μm for 10-nm channel length ITO transistor (IEDM 2020, First Author).

Service

Reviewer:

• Nature Communications
• IEEE Electron Device Letters (EDL)
• IEEE Transactions on Electron Devices (TED)
• Nano Letters
• Japanese Journal of Applied Physics
• Nano Research

Session Chair:

• EL07.13: 1D and 2D Materials—Technology Integration, 2023 MRS FALL MEETING & EXHIBIT

Outreach

Women in Electrical Engineering (WEE) student group, Stanford University (2023 - 2024)

• The organization fosters a sense of community among female EE students through programming that includes mentoring, community service, outreach, and social events.
• mentoring underrepresented students, facilitating cross-cultural communication, and fostering collaborative learning environments